The timing is specified as a delay after clock of between 2ns and 13ns. SPRS717F.pdf Table 5-15 specifies the TXD timing. Understanding the TXD spec for the AM335x is a little more complicated. A better hold description would be 'X1 rising to data hold'.) See SLLS901D.pdf table 9-23 for TLK110 TXD timing. It is improbable that this is what is meant since the setup time is 1.4ns. The way the t3 timing requirement is named, 'data hold to X1 rising', a 2ns hold time implies that the signal stop holding before the clock edge. (I assume I'm understanding the spec correctly. There is a setup requirement of 1.4ns and a hold time of 2ns. The TLK110 timing requirements are easy to understand for the TXD lines. Micrel's KSZ8021 for instance requires 8ns hold. I'm suspicious that the AM335x might not be guaranteed to work with a lot of RMII interface PHYs. The hold time on the TXD lines won't be met. I believe the AM335x is not guaranteed to work with the TLK110. For example, the AM335x timing requirements/characteristics, attached Ethernet PHY timing requirements/characteristics, and PCB propogation delays should be evaluated to determine if setup/hold requirements are valid for all input signals. Note: Customers need to perform timing analysis when connecting any peripheral devices to AM335x. By changing the AM335x RMII Reference Clock output default state in silicon revision 2.0, customers should be able to use RMI to boot from Ethernet if they use a PHY that can source the RMII Reference Clock. In silicon revision 1.0, these two issues prevented any option of supporting Ethernet boot when using RMII. This issue is described in Advisory 1.0.18. The default state used in silicon revision 1.0 would cause the output to be enabled as soon as the ROM code tried to use RMII to boot from Ethernet.

However, we are changing the default state of the AM335x RMII Reference Clock output to be disabled at reset. The change required to fix this issue would be a major re-design of the clocking architecture.

Txd tool 1.4.2 for free